Three Op Amp IA Designs vs. AD620 REV. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. CONNECTION DIAGRAM 8-Lead Plastic Mini-DIP (N), Cerdip (Q) and SOIC (R) Packages 1000. Furthermore,

The output of the mixer core is taken directly from its open collectors. The open collector outputs present a high impedance at the IF frequency. The conversion gain of the mixer depends directly on the impedance presented to these open collectors. In characterization, a 100 . load was presented to the part via a 2:1 impedance transformer. The device also features a power-down function. Application of a logic low at the PWDN pin allows normal operation. A high logic level at the PWDN pin shuts d

Adobe Systems 0–1300207782- 119FREQUENCY (MHz) AMPLITUDE ( dBFS) –10–20–30–40–50–60–70–80–90–100–110–1205101520fIN = 3.5MHz @ –1dBFSLNA = 6.VGAIN = 1VFILTER TUNEDHPF = 700kHz Figure 17. Typical FFT, AD9272/AD9273 USING THE INTEGRATED CROSSPOINT SWITCH (CW DOPPLER MODE) To examine the spectrum of the CW Doppler integrated crosspoint switch output, use the following procedure: 1. Complete the steps in the Configuring the Board and Using the Software for Testing sections to ensure that the board is

The AD9272/AD9273 data sheet, available at provides additional information and should be consulted when using the evaluation board. All documents and software tools are available at For any questions, send an email to highspeed.converters@analog.com. TYPICAL MEASUREMENT SETUP Adobe Systems 07782- 001 Figure 1. AD9272-65EBZ/AD9272-80KITZ/AD9273-50EBZ Evaluation Board and HSC-ADC-EVALCZ Data Capture Board TABLE OF CONTENTS Features ..................................................................

The AD9551 Revision D evaluation board is a compact, easy to use platform for evaluating all features of the AD9551 multiservice clock generator. The AD9551 accepts one or two reference input signals to synthesize one or two output signals. The AD9551 uses a fractional-N PLL that precisely translates the reference frequency to the desired output frequency. The input receivers and output drivers provide both single-ended and differential operation. Reference conditioning and switchover circuitry

The AD9843A’s signal chain consists of an input clamp, correlated double sampler (CDS), digitally controlled variable gain amplifier (VGA), black level clamp, and 10-bit A/D converter. Additional input modes are provided for processing analog video signals. The internal registers are programmed through a 3-wire serial digital interface. Programmable features include gain adjustment, black level adjustment, input configuration, and power- down modes. The AD9843A operates from a single 3 V power s

Its 140 MSPS encode rate capability and full power analog bandwidth of 300 MHz supports resolutions up to SXGA (1280 . 1024 at 75 Hz). The AD9883A includes a 140 MHz triple ADC with internal 1.25 V reference, a PLL, and programmable gain, offset, and clamp control. The user provides only a 3.3 V power supply, analog input, and HSYNC and COAST signals. Three-state CMOS outputs may be powered from 2.5 V to 3.3 V. The AD9883A’s on-chip PLL generates a pixel clock from HSYNC and COAST inputs. Pixel