The AD9843A’s signal chain consists of an input clamp, correlated double sampler (CDS), digitally controlled variable gain amplifier (VGA), black level clamp, and 10-bit A/D converter. Additional input modes are provided for processing analog video signals. The internal registers are programmed through a 3-wire serial digital interface. Programmable features include gain adjustment, black level adjustment, input configuration, and power- down modes. The AD9843A operates from a single 3 V power s

Its 140 MSPS encode rate capability and full power analog bandwidth of 300 MHz supports resolutions up to SXGA (1280 . 1024 at 75 Hz). The AD9883A includes a 140 MHz triple ADC with internal 1.25 V reference, a PLL, and programmable gain, offset, and clamp control. The user provides only a 3.3 V power supply, analog input, and HSYNC and COAST signals. Three-state CMOS outputs may be powered from 2.5 V to 3.3 V. The AD9883A’s on-chip PLL generates a pixel clock from HSYNC and COAST inputs. Pixel

A TCP/IP stack with integrated device driver and example code is provided in VisualDSP++® release 4.0. This evaluation kit was designed with an emphasis on modularity and expandability. With this EZ-KIT Lite, users can learn more about Analog Devices ADSP-BF537 hardware and software development and quickly prototype applications. The EZ-KIT Lite includes an ADSP-BF537 processor desktop evaluation board along with an evaluation suite of the VisualDSP++ development and debugging environment that i

Populate R406 and R407 with 0 . resistors and remove R415 and R416 to disconnect the default clock path inputs. In addition, populate C405 and C406 with a 0.1 .F capacitor and remove C409 and C410 to disconnect the default clock path outputs. The AD9515 has many pin- strappable options that are set to a default mode of operation. Consult the AD9515 data sheet for more information about these and other options. PDWN To enable the power-down feature, short P303 to the on position (AVDD) on the PDW

The output of the mixer core is taken directly from its open collectors. The open collector outputs present a high impedance at the IF frequency. The conversion gain of the mixer depends directly on the impedance presented to these open collectors. In characterization, a 100 . load was presented to the part via a 2:1 impedance transformer. The device also features a power-down function. Application of a logic low at the PWDN pin allows normal operation. A high logic level at the PWDN pin shuts d

The AD9551 Revision D evaluation board is a compact, easy to use platform for evaluating all features of the AD9551 multiservice clock generator. The AD9551 accepts one or two reference input signals to synthesize one or two output signals. The AD9551 uses a fractional-N PLL that precisely translates the reference frequency to the desired output frequency. The input receivers and output drivers provide both single-ended and differential operation. Reference conditioning and switchover circuitry

All trademarks are the property of their respective holders. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. ADSP-2186 FUNCTIONAL BLOCK DIAGRAM ADSP-2100 BASE SHIFTERMACALU ARITHMETIC UNI

Please follow all of the warnings on this product and its operating instructions. CAUTION: WARNING: To prevent the risk of electric shock and fire, do not expose this device to rain, humidity or intense heat sources (such as heaters or direct sunlight). Slots and openings in the device are provided for ventilation and to avoid overheating. Make sure the device is never placed on or near a textile surface that could block the openings. Also keep away from excessive dust, vibrations and shocks. PO

The AD9272/AD9273 data sheet, available at provides additional information and should be consulted when using the evaluation board. All documents and software tools are available at For any questions, send an email to highspeed.converters@analog.com. TYPICAL MEASUREMENT SETUP Adobe Systems 07782- 001 Figure 1. AD9272-65EBZ/AD9272-80KITZ/AD9273-50EBZ Evaluation Board and HSC-ADC-EVALCZ Data Capture Board TABLE OF CONTENTS Features ..................................................................

Cr, Cb: 0.7 Vp/p. Impedance: 75 Ohm. • S.VIDEO Connector: 4-pin mini DIN female. Standard: PAL : 15.625 kHz / 50 Hz - 625 lines. NTSC : 15.734 kHz / 59.94 Hz - 525 lines - 7.5 IRE. Level: Y : 1 Vp/p (0.7 V Luma + 0.3 V Sync.). C : 0.7 Vp/p (0.3 V Chroma Burst). Impedance: 75 Ohm. • COMPOSITE VIDEO Connector: BNC female. Standard: PAL : 15.625 kHz / 50 Hz - 625 lines. NTSC : 15.734 kHz / 59.94 Hz - 525 lines - 7.5 IRE. Level: 1 Vp/p (0.7 V Luma + 0.3 V Sync.). Impedance: 75 Ohm. • FRAME LOCK Conn