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Max. Unit CS1 set-up time tSU(CS1) 1000 Address set-up time before ALE tSU(A-ALE) 50 Address hold time after ALE th(ALE-A) 50 ALE pulse width tw(ALE) 80 ALE set-up time before read tSU(ALE-R) 0 ns ALE set-up time after read tSU(R-ALE) 50 Data output transfer time after read tPZV(R-Q) CL=150 pF 120 Data output floating transfer time after read tPVZ(R-Q) 0 70 CS1 hold time th(CS1) 1000 Read recovery time trec(W) 200 (1) Write mode VIH2 tsu(CS1) tsu(A-ALE) tw(ALE) th(ALE-A) tsu(ALE-W) tw(W) VIH1 VIL1 VIH1 VIL1 VIH1 VIL1 VIH1 VIH1 VIL1 VIL1 VIH1 VIL1 tsu(W-ALE) VIH1 VIL1 VIH1 VIL1 tsu(D-W) th(W-D) th(CS1) VIH2 CS1 A0 to A3 CS0 ALE D0 to D3 WR (Input) (2) Read mode VIH2 tsu(CS1) tsu(A-ALE) tw(ALE) th(ALE-A) tsu(ALE-R) VIH1 VIL1 VIH1 VIL1 VIH1 VIL1 VIH1 VIH1 VIL1 VIL1 VIH1 VIL1 tsu(R-ALE) VIH1 VIL1 VIH1 VIL1 tpzv(R-Q) tpvz(R-Q) th(CS1) VIH2 CS1 A0 to A3 CS0 ALE D0 to D3 RD (Input) Page - 5 MQ - 162 - 03 RTC - 72421 / 72423 2. When ALE is fixed at VDD Write mode ( VDD=5 V ± 0.5 V, RTC-72421;Ta=.10 °C to +70 °C, RTC-72423;Ta=.40 °C to +85 °C ) Item Symbol Condition Min. Max. Unit CS1 set-up time tSU(CS1) 1000 ns CS1 hold time th(CS1) 1000 Address set-up time before write tSU(A-W) 50 Address hold time after write th(W-A) 10 Write pulse width tw(W) 120 Data input set-up time before write tSU(D-W) 80 Data input hold time after write th(W-D) 10 Write recovery time trec(W) 200 Read mode ( VDD=5 V ± 0.5 V, RTC-72421;Ta=.10 °C to +70 °C, RTC-72423;Ta=.40 °C to +85 °C ) Item Symbol Condition Min. Max. Unit CS1 set-up time tSU(CS1) 1000 CS1 hold time th(CS1) 1000 Address set-up time before read tSU(A-R) 50 Address hold time after read th(R-A) 10 ns Data output transfer time after read tpzv(R-Q) CL=150 pF 120 Data output floating transfer time after read tpvz(R-Q) 0 70 Read recovery time trec(R) 200 (1) Write mode VIH2 tsu(CS1) tsu(A-W) tw(W) VIH1 VIL1 VIH1 VIL1 VIH1 VIL1 VIL1 VIH1 th(W-A) VIH1 VIL1 VIH1 VIL1 tsu(D-W) th(W-D) th(CS1) VIH2 CS1 A0 to A3 CS0 D0 to D3 WR (Input) (2) Read mode VIH2 tsu(CS1) tsu(A-R) VIH1 VIL1 VIH1 VIL1 VIH1 VIL1 VIL1 VIH1 th(R-A) VOH VOL VOH VOL tpzv(R-Q) tpvz(R-Q) th(CS1) VIH2 CS1 A0 to A3 CS0 D0 to D3 RD (Output) (3) Read/write recovery mode VIH1VIH1 RD,WR trec(R/W) Page - 6 MQ - 162 - 03 RTC - 72421 / 72423 .. Registers 1. Register table Address (Hex) A3 A2 A1 A0 Register name Data Count (BCD) Remarks D3 D2 D1 D0 0 0 0 0 0 S1 s8 s4 s2 s1 0 to 9 1-second digit register 1 0 0 0 1 S10 * s40 s20 s10 0 to 5 10-seconds digit register 2 0 0 1 0 MI1 mi8 mi4 mi2 mi1 0 to 9 1-minute digit register 3 0 0 1 1 MI10 * mi40 mi20 mi10 0 to 5 10-minute digit register 4 0 1 0 0 H1 h8 h4 h2 h1 0 to 9 1-hour digit register 5 0 1 0 1 H10 * PM/AM h20 h10 0 to1 or 2 10-hours digit register 6 0 1 1 0 D1 d8 d4 d2 d1 0 to 9 1-day digit register 7 0 1 1 1 D10 * * d20 d10 0 to 3 10-days digit register 8 1 0 0 0 MO1 mo8 mo4 mo2 mo1 0 to 9 1-month digit register 9 1 0 0 1 MO10 * * * mo10 0 to 1 10-months digit register A 1 0 1 0 Y1 y8 y4 y2 y1 0 to 9 1-year digit register B 1 0 1 1 Y10 y80 y40 y20 y10 0 to 9 10-years digit register C 1 1 0 0 W * w4 w2 w1 0 to 6 Day-of-the-week register D 1 1 0 1 CD 30s ADJ IRQ FLAG BUSY HOLD Control register D E 1 1 1 0 CE t1 t0 ITRPT/ STND MASK Control register E F 1 1 1 1 CF TEST 24/12 STOP RESET Control register F 2. Notes The counts at addresses 0 to C are all positive logic. Therefore, a register bit that is 1 appears as a high-level signal on the data bus. Data representation is BCD. Do not set an impossible date or time in the RTC. If such a value is set, the effect is unpredictable. When the power is turned on (before the RTC is initialized), the state of all bits is undefined. Therefore, write to all registers after power-on, to set initial values. For details of the initialization procedure, see "Using the RTC-72421/RTC-72423". The TEST bit of control register F is used by EPSON for testing. Operation cannot be guaranteed if 1 is written to this bit, so make sure that it is set to 0 during power-on initialization. 3. Functions of register bits (overview) Bit name Function * mark Not used. Writing to this bit has no effect; reading it always returns 0. Seconds to year digit All written BCD code. Day-of-the-week digit This is special (base 7) counter that increments each time the day digits are incremented. It counts from 0 to 6. Since the value in the counter bears no relationship to the day of the week, the user can choose the coding that relates the counter value to the day of the week. The following is just one example of this relationship. Count 0 1 2 3 4 5 6 Day Sunday Monday Tuesday Wednesday Thursday Friday Saturday PM/AM The PM/AM bit is 1 for p.m. times; 0 for a.m. times. This bit is valid only for 12-hour-clock mode (when the 24/12 bit is 0); in 24-hourclock mode (when the 24/12 bit is 1), this bit is always 0. 30-seconds ADJ Writing 1 to this bit executes a 30-seconds correction. IRQ FLAG The IRQ FLAG bit is set to 1 when an interrupt request is generated in fixed-perio...

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