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. BiCMOS technology Functional Description The CYV15G0404RB Independent Clock Quad HOTLink II™ Deserializing Reclocker is a point-to-point or point-to-multipoint communications building block enabling data transfer over a variety of high speed serial links including SMPTE 292 and SMPTE 259 video applications. It supports signaling rates in the range of 195 to 1500 Mbps for each serial link. The four channels are independent and can simultaneously operate at different rates. Each receive channel accepts serial data and converts it to 10-bit parallel characters and presents these characters to an Output Register. The received serial data can also be reclocked and retransmitted through the reclocker serial outputs. Figure 1, "HOTLink II™ System Connections," on page 2 illustrates typical connections between independent video coprocessors and corresponding CYV15G0404RB Reclocking Deserializer and CYV15G0403TB Serializer chips. The CYV15G0404RB is SMPTE-259M and SMPTE-292M compliant according to SMPTE EG34-1999 Pathological Test Requirements. As a second generation HOTLink device, the CYV15G0404RB extends the HOTLink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility (data and BIST) with other HOTLink devices. Each channel of the CYV15G0404RB Quad HOTLink II device accepts a serial bit-stream from one of two selectable PECL-compatible differential line receivers, and using a completely integrated Clock and Data Recovery PLL, recovers the timing information necessary for data reconstruction. The device reclocks and retransmits recovered bit-stream through the reclocker serial outputs. It also deserializes the recovered serial data and presents it to the destination host system. Each channel contains an independent BIST pattern checker. This BIST hardware enables at speed testing of the high-speed serial data paths in each receive section of this device, each transmit section of a connected HOTLink II device, and across the interconnecting links. The CYV15G0404RB is ideal for SMPTE applications where different data rates and serial interface standards are necessary for each channel. Some applications include multi-format routers, switchers, format converters, SDI monitors, and camera control units. Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 38-02102 Rev. *C Revised February 16, 2007 [+] Feedback 10 10 10 10 Serial Links Independent CYV15G0403TB Independent Reclocking Deserializer Serializer Channel CYV15G0404RB Channel Outputs Reclocked 10 10 10 10 Serial Links Independent CYV15G0403TB Independent Reclocking Deserializer Serializer Channel CYV15G0404RB Channel Outputs Reclocked CYV15G0404RB Figure 1. HOTLink II™ System Connections Video Coprocessor 10 10 10 10 Video Coprocessor Reclocked Outputs CYV15G0404RB Deserializing Reclocker Logic Block Diagram x10 Deserializer Reclocker RX RXDA[9:0]TRGCLKA± x10 Deserializer Reclocker RX RXDB[9:0]TRGCLKB± x10 Deserializer Reclocker RX RXDC[9:0]TRGCLKC± x10 Deserializer Reclocker RX RXDD[9:0]TRGCLKD± ROUTA1± ROUTA2± INA1±INA2± ROUTB1±ROUTB2± INB1±INB2± ROUTC1± ROUTC2± INC1± INC2± ROUTD1± ROUTD2± IND1± IND2± Document #: 38-02102 Rev. *C Page 2 of 27 [+] Feedback CYV15G0404RB = Internal Signal Reclocking Deserializer Path Block Diagram RESET TRGCLKA LDTDEN INSELA INA1+ INA1– INA2+ INA2– ULCA SPDSELA RECLKOA REPDOA Clock & Data RecoveryPLL Shifter 10 RXDA[9:0] Receive SignalMonitor OutputRegister RXCLKA+ RXCLKA– .2 RXPLLPDA RXRATEA 10 BIST LFSR10 RXBISTA[1:0] SDASEL[2..1]A[1:0] ROUTA1+ ROUTA1– ROUTA2+ ROUTA2– ROE[2..1]A x2 TRGRATEA BISTSTA Character-Rate Clock A Reclocker Register Recovered Character Clock Recovered Serial Data Clock Multiplier AOutput PLL ROE[2..1]A JTAG BoundaryScan Controller TRST TMS TCLK TDI TDO LFIA TRGCLKB LDTDEN Clock & Data RecoveryPLL Shifter 10 Receive SignalMonitor OutputRegister .2 RXPLLPDB RXRATEB 10 BIST LFSR10 RXBISTB[1:0] SDASEL[2..1]B[1:0] ROE[2..1]B x2 TRGRATEB Character-Rate Clock B Reclocker Register Recovered Character Clock Recovered Serial Data Clock Multiplier BOutput PLL ROE[2..1]B LFIB INSELB RXDB[9:0] INB1+ INB1– BISTSTB INB2+ INB2– RXCLKB+ ULCB RXCLKB– SPDSELB ROUTB1+ ROUTB1– ROUTB2+ ROUTB2– RECLKOB REPDOB Document #: 38-02102 Rev. *C Page 3 of 27 [+] Feedback CYV15G0404RB Reclocking Deserializer Path Block Diagram (continued) = Internal Signal TRGCLKC LDTDEN Clock & Data RecoveryPLL Shifter 10 Receive SignalMonitor OutputRegister .2 RXPLLPDC RXRATEC 10 BIST LFSR10 RXBISTC[1:0] SDASEL[2..1]C[1:0] ROE[2..1]C x2 TRGRATEC Character-Rate Clock C Reclocker Register Recovered Character Clock Recovered Serial Data Clock Multiplier COutput PLL ROE[2..1]C LFIC INSELC RXDC[9:0] INC1+ INC1– BISTSTC INC2+ INC2– RXCLKC+ ULCC RXCLKC– SPDSELC ROUTC1+ ROUTC1– ROUTC2+ ROUTC2– RECLKOC REPDOC TRGCLKD LDTDEN Clock & Data RecoveryPLL Shifter 10 Receive SignalMonitor OutputRegister .2 RXPLLPDD RXRATED 10 BIST LFSR10 RXBISTD[1:0] SDA...