Low power, 350 nA RTC current . Capacitor or battery backup for RTC ¦ Watchdog timer ¦ Clock alarm with programmable interrupts ¦ Hands off automatic STORE on power down with only a small capacitor ¦ STORE to QuantumTrap™ initiated by software, device pin, or on power down ¦ RECALL to SRAM initiated by software or on power up ¦ Infinite READ, WRITE, and RECALL cycles ¦ High reliability . Endurance to 200K cycles . Data retention: 20 years at 55°C ¦ Single 3V operation with tolerance of +20%, –10

XBUF CPLL SPLL UPLL OSC. CPUCLK CLKA CLKB CLKC CLKD MUX OE CLKF /1,2,4 /1,2,3,4,5,6 /8,10,12,13 /20,24,26,40/48,52,96,104 /2,3,4 /1,2,4,8 (8 BIT) (8 BIT) (10 BIT) Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 38-07189 Rev. *C Revised September 16, 2008 [+] Feedback CY2291 Pinouts Pin Definitions Figure 1. CY2291- 20-pin SOIC 32XOUT 32K CLKC VDD GND XTALIN XTALOUT XBUF CLKD CPUCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 32XI

*B Revised October 26, 2005 [+] Feedback CY25566 Pin Description Pin Name Type Description 1 XIN/CLKIN I Clock or Crystal connection input. Refer to Table 1, Table 2, and Table 3 for input frequency range selection. 2 REFOFF I Input pin enables REFOUT clock at pin 3. REFOFF 400K. internal pull-up resistor. Logic “0” enables REFOUT, logic “1” disables REFOUT. Default = disabled. 3 REFOUT O Buffered, non-modulated output clock derived from XIN/CLKIN input frequency. There is a 180° phase shift fro

. *B Revised April 11, 2006 [+] Feedback CY25818/19 . Pin Description Pin Name Description 1 XIN/CLK Clock, Crystal, or Ceramic Resonator Input Pin. 2 Vss Power Supply Ground. 3 S0 Digital Spread% Control Pin. 3-Level input (H-M-L). Default = M. 4 SSCLK Modulated Spread Spectrum Output Clock. The output frequency is referenced to input frequency. Refer to Table 2 for the amount of modulation (Spread%). 5 REFCLK Unmodulated Reference Clock Output. The unmodulated output frequency is the same as t

–65°C to + 150°C Input Voltage Relative to Vdd:.............................. Vdd + 0.3V Table 4. DC Electrical Characteristics Vdd = 3.3V ±10%, TA = 0°C to +70°C and CL = 15 pF (unless otherwise noted) Parameter Description Conditions Min. Typ. Max. Unit Vdd Power Supply Range 2.97 3.3 3.63 V VINH Input HIGH Voltage S0 Input 0.85 Vdd Vdd Vdd V VINM Input MIDDLE Voltage S0 Input 0.40 Vdd 0.50 Vdd 0.60 Vdd V VINL Input LOW Voltage S0 Input 0.0 0.0 0.15 Vdd V VOH1 Output HIGH Voltage IOH = 4 ma, S

P u ll-u p Freq. Phase Modulating VCO Post CLKOUT Detector Charge Pump Waveform Dividers Divider Feedback Divider PLL GND VDD . M N Clock Input (SSCG Output) REFOUT Logic Control SDATA SCLOCK PWRDWN# Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-07531 Rev. ** Revised March 18, 2003 [+] Feedback CY25822-2 Pin Description Pin No. Pin Name Pin Type Pin Description 1 CLKIN Input 48-MHz or 66-MHz Clock Input. 2 VDD Power Power Supply fo

Selectable skew to 18 ns . Inverted and non-inverted . Operation at 1.2 and 1.4 input frequency . Operation at 2x and 4x input frequency (input as low as 3.75 MHz) ¦ Zero input to output delay ¦ 50% duty cycle outputs ¦ Outputs drive 50. terminated lines ¦ Low operating current ¦ 32-pin PLCC/LCC package ¦ Jitter < 200 ps peak-to-peak (< 25 ps RMS) Functional Description The CY7B991 and CY7B992 Programmable Skew Clock Buffers (PSCB) offer user selectable control over system clock functions. These

terminated lines ¦ Low operating current ¦ 24-pin SOIC package ¦ Jitter:<200 ps peak to peak, <25 ps RMS Functional Description The CY7B9910 and CY7B9920 Low Skew Clock Buffers offer low skew system clock distribution. These multiple output clock drivers optimize the timing of high performance computer systems. Each of the eight individual drivers can drive terminated transmission lines with impedances as low as 50.. They deliver minimal and specified output skews and full swing logic levels (CY

Document Number: 38-07408 Rev. *D Page 4 of 14 [+] Feedback CY7B9911V 3.3V RoboClock+™ Document Number: 38-07408 Rev. *D Page 5 of 14 Operational Mode Descriptions Figure 2 shows the LVPSCB configured as a zero skew clock buffer. In this mode the CY7B9911V is used as the basis for a low skew clock distribution tree. When all the function select inputs (xF0, xF1) are left open, each of the outputs are aligned and drive a terminated transmission line to an independent load. The FB input is tied to

The frequency of the REF and FB inputs are fNOM/2 or fNOM/4 when the part is configured for a frequency multiplication by using a divided output as the FB input. 3. When the FS pin is selected HIGH, the REF input must not transition upon power up until VCC has reached 4.3V. Document Number: 38-07138 Rev. *B Page 3 of 19 [+] Feedback CY7B991 CY7B992 Figure 1 shows the typical outputs with FB connected to a zero skew output.[4] Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output t –