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Фрагмент инструкции
The microcontroller will also change the state of the mute if the monitor button is depressed (SW402), assuming that this function has been enabled in the programming Pin 13 is connected to Q414, Q415 via R446, which mutes the TDA7233IC. DETAILED FUNCTIONAL DESCRIPTION Issue 1.0 Page 5-4 03/01 SP200/210 Maxon SP200/210 Radio Battery Low Indicator Circuit When the battery voltage drops below 5.6 VDC a Battery Low indication is given. Due to the volts drop across D403, a voltage below 5.6V on the battery gives a voltage less than 5V on the base of Q405. , Q405 switches on its when base is below 5v (current flow through R413), which switches on Q404, so driving pin 52 of the microcontroller low (normally tied high). The micro controller disables the transmitter and at the same time enables the red LED and sends an alert tone to warn the user. The battery should be replaced or recharged at this time (one transmission is allowed after the low battery warning). LEDs and indicators The red and green LEDs are switched on, via Q407and Q411, by control lines from the microcontroller. Both the red and green LEDs being lit indicate the condition ‘busy’ i.e. orange. Both the LCD and backlight are driven from the microcontroller. The alert tones are generated in the microcontroller and are fed through a filter to the volume control via link 27. There is an option of routing the tones directly to the audio amp via link28. 5.5 Common RF Circuits PLL Synthesiser The PLL synthesiser circuit is common to both the transmitter and receiver. The synthesiser comprises: TCXO Loop Filter Data IC 2 PLL Tx or Rx VCO ~ Charge Pump DC -DC Converter RF Out Figure 5-2 – Synthesiser Block Diagram 12.8 MHz TCXO The TCXO contains a crystal oscillator, which has 2-stage thermistor network compensation, and a modulation port. Accuracy is +/-2.5 PPM from -30°C to +60°C. Frequency adjustment is provided by TC701. VCO The VCO is configured as a Colpitts oscillator using transistor Q202, varactor diodes D201 / 202, frequency setting inductor L203 and associated components. Cascade bias is provided by Q201. The frequency of operation is controlled by reverse biasing D201 in the range of 1 to 12 V dc (from the PLL). During receive Q9 is switched on by the Rx enable (active low), so switching D203 in circuit (via Q203), which puts C208 (variable capacitor) in parallel with the varactor diodes and adjustable inductor. Issue 1.0 DETAILED FUNCTIONAL DESCRIPTION 03/01 Page 5-5 Maxon SP200/210 Radio SP200/210 In transmit the VCO has modulation from the audio processing circuitry applied to D202. C204 is used to provide compensation for non-linearity caused by the modulation diode and maintains a constant modulation regardless of the frequency of operation. PLL IC The reference frequency from the TCXO, at 12.8 MHz, is connected to pin 20 of IC2 (MC145191). The appropriate VCO is connected to pin 11. The external reference frequency, TCXO input, is divided by the reference divider (REFDIV), which is set to divide by 2048 for 12.5kHz or 25kHz channels (6.25kHz) or to divide by 2560 for 20kHz channels (5kHz). This is known as the reference frequency, Fr. The comparison frequency is determined by the settings which are stored within the EEPROM (IC404). Choice of these comparison frequencies means that the minimum step size of the synthesiser is either 5kHz or 6.25kHz and therefore, 12.5kHz, 20kHz and 25kHz channel spacings can be accommodated. IC2 is programmed on pin 19, to obtain the desired frequency, by serial data from the microcontroller (IC403 pin 21). IC2 Pin 19 is the data input and pin 18 is the clock input and pin 17 is the PLL enable line. The VCO frequency, Fin, is divided down by the programmable divider (64/65 prescaler VARDIV) to, again, produce 5kHz or 6.25kHz. This frequency is known as the variable frequency, Fv. In the phase/frequency comparator, the phase difference between the reference frequency, Fr, and the VCO signal, Fv, is compared. When Fv = Fr, the phase detector output (pins 3 and 4, IC2) produces narrow negative pulses and Fv and Fr pulse widths are identical. When Fv > Fr, pin 4 (V) pulses negative, with pin 3 (R) remaining high. When Fv < Fr, pin 3 (R) pulses negative with pin 4 (V) remaining high. The signal at pins 3 and 4 is smoothed by the loop filter and applied to the VCO. Out-of-Lock Detector The out-of-lock detector output remains essentially high with narrow low-going pulses when in lock. The output pulses low when Fr and Fv are out of phase or at a different frequency (results in wider pulses). These pulses at pin 2 are buffered by Q5 and then integrated by R1 and C11. The resultant voltage is fed to the microcontroller, IC403, pin 53. IC2 has two output ports: Port A pin 16 Configurable digital port, which is used as tx enable 2, which controls the application of volts to the PA stage. Port B pin 15 Open drain digital output, which is used as a power save control. Pin 13 labelled test2 allows the technician to see t...
Эта инструкция также подходит к моделям:Рации - SP210 (2.86 mb)
Рации - SP200 (2.86 mb)
Рации - SP200 (2.86 mb)
Рации - SP200 (2.86 mb)