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К этому устройству также есть другие инструкции:
Компьютеры - Intel® Desktop Board DH61CR (3.29 mb)
Компьютеры - Intel® Desktop Board DH61CR (1.79 mb)
Фрагмент инструкции
If the POST fails, execution stops and the last POST code generated is left at port 80h. This code is useful for determining the point where an error occurred. Displaying the POST codes requires a POST card that can interface with the Low Pin Count (LPC) Debug header. The POST card can decode the port and display the contents on a medium such as a seven-segment display. Refer to the location of the LPC Debug header in Figure 1. The following tables provide information about the POST codes generated by the BIOS: • Table 40 lists the Port 80h POST code ranges • Table 41 lists the Port 80h POST codes themselves • Table 42 lists the Port 80h POST sequence NOTE In the tables listed above, all POST codes and range values are listed in hexadecimal. Table 40. Port 80h POST Code Ranges Range Subsystem 0x00 – 0x05 Entering SX states S0 to S5. 0x10, 0x20, 0x30, 0x40, 0x50 Resuming from SX states. 0x10 –0x20 – S2, 0x30 – S3, etc. 0x08 – 0x0F Security (SEC) phase 0x11 – 0x1F PEI phase pre MRC execution 0x21 – 0x29 MRC memory detection 0x2A – 0x2F PEI phase post MRC execution 0x31 – 0x35 Recovery 0x36 – 0x3F Platform DXE driver 0x41 – 0x4F CPU Initialization (PEI, DXE, SMM) 0x50 – 0x5F I/O buses: PCI, USB, ATA, etc. 0x5F is an unrecoverable error. Start with PCI. 0x60 – 0x6F BDS 0x70 – 0x7F Output devices: All output consoles. 0x80 – 0x8F For future use 0x90 – 0x9F Input devices: Keyboard/Mouse. 0xA0 – 0xAF For future use 0xB0 – 0xBF Boot Devices: Includes fixed media and removable media. Not that critical since consoles should be up at this point. 0xC0 – 0xCF For future use 0xD0 – 0xDF For future use 0xF0 – 0xFF Table 41. Port 80h POST Codes Port 80 Code Progress Code Enumeration ACPI S States 0x00,0x01,0x02,0x03,0x04,0x05 Entering S0, S2, S3, S4, or S5 state 0x10,0x20,0x30,0x40,0x50 Resuming from S2, S3, S4, S5 Security Phase (SEC) 0x08 Starting BIOS execution after CPU BIST 0x09 SPI prefetching and caching 0x0A Load BSP microcode 0x0B Load APs microcodes 0x0C Platform program baseaddresses 0x0D Wake Up All APs 0x0E Initialize NEM 0x0F Pass entry point of the PEI core PEI before MRC PEI Platform driver 0x11 Set bootmode, GPIO init 0x12 Early chipset register programming including graphics init 0x13 Basic PCH init, discrete device init (1394, SATA) 0x14 LAN init 0x15 Exit early platform init driver PEI SMBUS 0x16 SMBUSriver init 0x17 Entry to SMBUS execute read/write 0x18 Exit SMBUS execute read/write PEI CK505 Clock Programming 0x19 Entry to CK505 programming 0x1A Exit CK505 programming PEI Over-Clock Programming 0x1B Entry to entry to PEI over-clock programming 0x1C Exit PEI over-clock programming Memory 0x21 MRC entry point 0x23 Reading SPD from memory DIMMs 0x24 Detecting presence of memory DIMMs 0x27 Configuring memory 0x28 Testing memory 0x29 Exit MRC driver PEI after MRC 0x2A Start to Program MTRR Settings 0x2B Done Programming MTRR Settings continued Table 41. Port 80h POST Codes (continued) Port 80 Code Progress Code Enumeration PEIMs/Recovery 0x31 Crisis Recovery has initiated 0x33 Loading recovery capsule 0x34 Start recovery capsule / valid capsule is found CPU Initialization CPU PEI Phase 0x41 Begin CPU PEI Init 0x42 XMM instruction enabling 0x43 End CPU PEI Init CPU PEI SMM Phase 0x44 Begin CPU SMM Init smm relocate bases 0x45 Smm relocate bases for APs 0x46 End CPU SMM Init CPU DXE Phase 0x47 CPU DXE Phase begin 0x48 Refresh memory space attributes according to MTRRs 0x49 Load the microcode if needed 0x4A Initialize strings to HII database 0x4B Initialize MP support 0x4C CPU DXE Phase End CPU DXE SMM Phase 0x4D CPU DXE SMM Phase begin 0x4E Relocate SM bases for all APs 0x4F CPU DXE SMM Phase end I/O Buses 0x50 Enumerating PCI buses 0x51 Allocating resources to PCI bus 0x52 Hot Plug PCI controller initialization USB 0x58 Resetting USB bus 0x59 Reserved for USB ATA/ATAPI/SATA 0x5A Resetting PATA/SATA bus and all devices 0x5B Reserved for ATA continued Table 41. Port 80h POST Codes (continued) Port 80 Code Progress Code Enumeration BDS 0x60 BDS driver entry point initialize 0x61 BDS service routine entry point (can be called multiple times) 0x62 BDS Step2 0x63 BDS Step3 0x64 BDS Step4 0x65 BDS Step5 0x66 BDS Step6 0x67 BDS Step7 0x68 BDS Step8 0x69 BDS Step9 0x6A BDS Step10 0x6B BDS Step11 0x6C BDS Step12 0x6D BDS Step13 0x6E BDS Step14 0x6F BDS return to DXE core (should not get here) Keyboard (PS/2 or USB) 0x90 Resetting keyboard 0x91 Disabling the keyboard 0x92 Detecting the presence of the keyboard 0x93 Enabling the keyboard 0x94 Clearing keyboard input buffer 0x95 Instructing keyboard controller to run Self Test (PS/2 only) Mouse (PS/2 or USB) 0x98 Resetting mouse 0x99 Detecting mouse 0x9A Detecting presence of mouse 0x9B Enabling mouse Fixed Media 0xB0 Resetting fixed media 0xB1 Disabling fixed media 0xB2 Detecting presence of a fixed media (IDE hard drive detection, etc.) 0xB3 Enabling/configuring a fixed media continued Table 41. Port 80h POST Codes (continued) Port 80 Code Progress Code Enumeration R...