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Pin Definition Figure 1. CY24713, 8-Pin SOIC Name Number Description XIN 1 Reference Crystal Input VDD 2 3.3V Voltage Supply VCXO 3 Input Analog Control for VCXO VSS 4 Ground CLK_B 5 13.5-MHz Clock Output CLK_A 6 4.9152-MHz Clock Output CLK_C 7 27-MHz Clock Output XOUT[1] 8 Reference Crystal Output Note 1. Float XOUT if XIN is externally driven. Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Document #: 38-07396 Rev. *A Revised May 22, 2008 [+] Feedback CY24713 Absolute Maximum Conditions Parameter Description Min Max Unit VDD Supply Voltage –0.5 7.0 V TS Storage Temperature[2] –65 125 °C TJ Junction Temperature – 125 °C Digital Inputs VSS – 0.3 VDD + 0.3 V Digital Outputs referred to VDD VSS – 0.3 VDD + 0.3 V Electrostatic Discharge – 2000 V Analog Input –0.5 7.0 V Pullable Crystal Specifications Parameter Description Condition Min Typ. Max Unit FNOM Nominal crystal frequency Parallel resonance, fundamental mode, AT cut – 27 – MHz CLNOM Nominal load capacitance – 14 – pF R1 Equivalent series resistance (ESR) Fundamental mode – – 25 . R3/R1 Ratio of third overtone mode ESR to fundamental mode ESR Ratio used because typical R1 values are much less than the maximum spec. 3 – – DL Crystal drive level No external series resistor assumed – 0.5 2.0 mW F3SEPHI Third overtone separation from 3*FNOM High side 300 – – ppm F3SEPLO Third overtone separation from 3*FNOM Low side – – –150 ppm C0 Crystal shunt capacitance – – 7 pF C0/C1 Ratio of shunt to motional capacitance 180 – 250 C1 Crystal motional capacitance 14.4 18 21.6 pF Recommended Operating Conditions Parameter Description Min Typ. Max Unit VDD Operating Voltage 3.135 3.3 3.465 V TA Ambient Temperature 0 – 70 °C CLOAD Max. Load Capacitance – – 15 pF tPU Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 – 500 ms DC Electrical Characteristics Parameter Description Conditions Min Typ. Max Unit IOH Output High Current VOH = VDD – 0.5, VDD = 3.3V 12 24 – mA IOL Output Low Current VOL = 0.5, VDD = 3.3V 12 24 – mA CIN Input Capacitance – – 7 pF IIZ Input Leakage Current – 5 – .A f.XO VCXO pullability range ±150 – – ppm VVCXO VCXO input range 0 – VDD V IVDD Supply Current – 25 30 mA Note 2. Rated for 10 years Document #: 38-07396 Rev. *A Page 2 of 5 [+] Feedback CY24713 AC Electrical Characteristics (VDD = 3.3V) Parameter[3] Description Conditions Min Typ. Max Unit DC Output Duty Cycle Duty Cycle is defined in Figure 3 50% of VDD 45 50 55 % ER0 Rising Edge Rate Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF Figure 4. 0.8 1.4 – V/ns EF1 Falling Edge Rate Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF Figure 4. 0.8 1.4 – V/ns t9 Clock Jitter Peak-Peak period jitter maximum absolute jitter – 200 250 ps t10 PLL Lock Time – – 3 ms Figure 2. Test Circuit 0.1 .F VDD CLK out C LOAD OUTPUTS GND Figure 3. Duty Cycle Definition; DC = t2/t1 t1 t2 CLK 50% 50% Figure 4. Rise and Fall Time Definitions: ER = 0.6 x VDD/t3, EF = 0.6 x VDD/t4 t3 t4 CLK 80% 20% Note 3. Not 100% tested Document #: 38-07396 Rev. *A Page 3 of 5 [+] Feedback CY24713 Ordering Information Ordering Code Package Type Operating Range Operating Voltage CY24713SC[4] 8-pin SOIC Commercial 3.3V CY24713SCT[4] 8-pin SOIC Commercial 3.3V Pb-free CY24713SXC[4] 8-pin SOIC Commercial 3.3V CY24713SXCT[4] 8-pin SOIC-Tape and Reel Commercial 3.3V CY24713KSXC 8-pin SOIC Commercial 3.3V CY24713KSXCT 8-pin SOIC-Tape and Reel Commercial 3.3V Package Diagram Figure 5. 8-Lead (150-Mil) SOIC S8 PIN1ID 41 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME 0.150[3.810] RECTANGULAR ON MATRIX LEADFRAME 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG. 58 0.189[4.800] 0.010[0.254] 0.004[0.102] X 45° SEATING PLANE 0.196[4.978] 0.016[0.406] 0.061[1.549] 0.068[1.727] 0.050[1.270] BSC 0.0075[0.190] 0.004[0.102] 0°~8° 0.016[0.406] 0.0098[0.249] 0.0098[0.249] 0.035[0.889] 51-85066 *C 0.0138[0.350] 0.0192[0.487] Note 4. Not recommended for new designs. Document #: 38-07396 Rev. *A Page 4 of 5 [+] Feedback CY24713 Document History Page Document Title: CY24713 Set-top Box Clock Generator with VCXODocument Number: 38-07396 REV. ECN No. Orig. ofChange Submission Date Description of Change ** 333175 RGL See ECN New Data Sheet *A 2440886 AESA See ECN Updated template. Added Note “Not recommended for new designs.” Added part number CY24713KSXC, and CY24713KSXCT in ordering information table. Replaced Lead-Free with Pb-Free. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Solutions PSoC psoc.cypress.com General psoc.cypress.com/solutions Clocks & Buffers clock...