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Инструкция по эксплуатации Cypress, модель CY25818

Производитель: Cypress
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. *B Revised April 11, 2006 [+] Feedback CY25818/19 . Pin Description Pin Name Description 1 XIN/CLK Clock, Crystal, or Ceramic Resonator Input Pin. 2 Vss Power Supply Ground. 3 S0 Digital Spread% Control Pin. 3-Level input (H-M-L). Default = M. 4 SSCLK Modulated Spread Spectrum Output Clock. The output frequency is referenced to input frequency. Refer to Table 2 for the amount of modulation (Spread%). 5 REFCLK Unmodulated Reference Clock Output. The unmodulated output frequency is the same as the input frequency. 6 PD# Power-Down Control Pin. Default = H (Vdd). 7 Vdd Positive Power Supply. 8 XOUT Clock, Crystal, or Ceramic Resonator Output Pin. Leave this pin unconnected if an external clock is used at XIN pin. Overview The Cypress CY25818/19 products are Spread Spectrum Clock Generator (SSCG) ICs used for the purpose of reducing EMI found in today’s high-speed digital electronic systems. The devices use a Cypress proprietary phase-locked loop (PLL) and Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the input clock. By frequency modulating the clock, the measured EMI at the fundamental and harmonic frequencies is greatly reduced. This reduction in radiated energy can significantly reduce the cost of complying with regulatory agency requirements and improve time to market without degrading system performance. The input frequency range is 8–16 MHz for the CY25818 and 16–32 MHz for the CY25819. Both products accept external clock, crystal, or ceramic resonator inputs. The CY25818/19 provide separate modulated (SSCLK) and unmodulated reference (REFCLK) clock outputs which are the same frequency as the input clock frequency. Down spread frequency modulation can be selected by the user, based on three discrete values of Spread%. A separate power down function is also provided. Table 2. Spread% Selection The CY25818/19 products are available in an 8-pin SOIC (150-mil) package with a commercial operating temperature range of 0–70°C. Contact Cypress for availability of –40 to +85°C industrial temperature range operation or TSSOP package versions. Refer to the CY25568, CY25811, CY25812, and CY25814 products for other functions such as clock multiplication of 1., 2., or 4. to generate a wide range of Spread Spectrum output clocks from 4 to 128 MHz. Input Frequency Range and Selection CY25818/19 input frequency range is 8–32 MHz. This range is divided into two segments, as given in Table 1. Table 1. Input and Output Frequency Selection Product Input/Output Frequency Range CY25818 8–16 MHz CY25819 16–32 MHz Spread% Selection CY25818/19 SSCG products provide Down-Spread frequency modulation. The amount of Spread% is selected by using 3-Level S0 digital input. Spread% values are given in Table 2. XIN (MHz) Product S0 = 1 S0 = 0 S0 = M Down (%) Down (%) Down (%) 8–10 CY25818 –3.0 –2.2 –0.7 10–12 CY25818 –2.7 –1.9 –0.6 12–14 CY25818 –2.5 –1.8 –0.6 14–16 CY25818 –2.3 –1.7 –0.5 16–20 CY25819 –3.0 –2.2 –0.7 20–24 CY25819 –2.7 –1.9 –0.6 24–28 CY25819 –2.5 –1.8 –0.6 28–32 CY25819 –2.3 –1.7 –0.5 Document #: 38-07362 Rev. *B Page 2 of 7 [+] Feedback CY25818/19 3-Level Digital Inputs S0 digital input is designed to sense three logic levels designated as HIGH “1,” LOW “0,” and MIDDLE “M.” With this 3-Level digital input logic, the 3-Level logic is able to detect three different logic levels. The S0 pin includes an on-chip 20K (10K/10K) resistor divider. No external application resistors are needed to implement 3-Level logic, as follows. Logic Level “0”: 3-Level logic pin connected to GND. Logic Level “M”: 3-Level logic pin left floating (no connection.) Logic Level “1”: 3-Level logic pin connected to Vdd. Figure 1 illustrates how to implement 3-Level Logic. LO G IC LO G IC LO G IC LO W (0) M IDDL E (M ) HIG H (H ) VDD S0 S0 S0 to V S S UNCO N N E C TED to V DD VSS Figure 1. 3-Level Logic Table 3. Modulation Rate Divider Ratios Modulation Rate Spread Spectrum Clock Generators utilize frequency modulation (FM) to distribute energy over a specific band of frequencies. The maximum frequency of the clock (fmax) and minimum frequency of the clock (fmin) determine this band of frequencies. The time required to transition from fmin to fmax and back to fmin is the period of the Modulation Rate, Tmod. The Modulation Rates of SSCG clocks are generally referred to in terms of frequency, and fmod = 1/Tmod. The input clock frequency, fin, and the internal divider determine the Modulation Rate. In the case of CY25818/19 devices, the (Spread Spectrum) Modulation Rate, fmod, is given by the following formula: fmod = fIN/DR where fmod is the Modulation Rate, fIN is the Input Frequency, and DR is the Divider Ratio, as given in Table 3. Product Input Frequency Range Divider Ratio (DR) CY25818 8–16 MHz 256 CY25819 16–32 MHz 512 Maximum Ratings[1, 2] Input Voltage Relative to Vss:............................... Vss + 0.3V Operating Temperature:................................... 0°C to + 70°C Supply Voltage (Vdd): ......