Оценок - 3, средний балл: 4.7
(
)
)
|
Фрагмент инструкции
13 1 Overview .................................................................................................................. 14 1.1 General RapidIO System......................................................................................... 14 1.2 RapidIO Feature Support in SRIO .............................................................................. 17 1.3 Standards .......................................................................................................... 18 1.4 External Devices Requirements ................................................................................. 18 2 SRIO Functional Description....................................................................................... 19 2.1 Overview............................................................................................................ 19 2.2 SRIO Pins .......................................................................................................... 24 2.3 Functional Operation.............................................................................................. 24 3 Logical/Transport Error Handling and Logging ............................................................. 73 4 Interrupt Conditions................................................................................................... 74 4.1 CPU Interrupts ..................................................................................................... 74 4.2 General Description ............................................................................................... 74 4.3 Interrupt Condition Control Registers........................................................................... 75 4.4 Interrupt Status Decode Registers .............................................................................. 83 4.5 Interrupt Generation............................................................................................... 85 4.6 Interrupt Pacing.................................................................................................... 85 4.7 Interrupt Handling ................................................................................................. 86 5 SRIO Registers.......................................................................................................... 88 5.1 Introduction......................................................................................................... 88 5.2 Peripheral Identification Register (PID)......................................................................... 99 5.3 Peripheral Control Register (PCR) ............................................................................ 100 5.4 Peripheral Settings Control Register (PER_SET_CNTL)................................................... 101 5.5 Peripheral Global Enable Register (GBL_EN) ............................................................... 104 5.6 Peripheral Global Enable Status Register (GBL_EN_STAT) .............................................. 105 5.7 Block n Enable Register (BLKn_EN).......................................................................... 106 5.8 Block n Enable Status Register (BLKn_EN_STAT) ......................................................... 107 5.9 RapidIO DEVICEID1 Register (DEVICEID_REG1) ......................................................... 108 5.10 RapidIO DEVICEID2 Register (DEVICEID_REG2) ......................................................... 109 5.11 Packet Forwarding Register n for 16b DeviceIDs (PF_16B_CNTLn)..................................... 110 5.12 Packet Forwarding Register n for 8b DeviceIDs (PF_8B_CNTLn)........................................ 111 5.13 SERDES Receive Channel Configuration Registers n (SERDES_CFGRXn_CNTL)................... 112 5.14 SERDES Transmit Channel Configuration Registers n (SERDES_CFGTXn_CNTL) .................. 114 5.15 SERDES Macro Configuration Register n (SERDES_CFGn_CNTL)..................................... 116 5.16 DOORBELLn Interrupt Status Register (DOORBELLn_ICSR) ............................................ 117 5.17 DOORBELLn Interrupt Clear Register (DOORBELLn_ICCR) ............................................. 118 5.18 RX CPPI Interrupt Status Register (RX_CPPI_ICSR) ...................................................... 119 5.19 RX CPPI Interrupt Clear Register (RX_CPPI_ICCR) ....................................................... 120 5.20 TX CPPI Interrupt Status Register (TX_CPPI_ICSR)....................................................... 121 5.21 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR)........................................................ 122 5.22 LSU Status Interrupt Register (LSU_ICSR) .................................................................. 123 5.23 LSU Clear Interrupt Register (LSU _ICCR) .................................................................. 124 5.24 Error, Reset, and Special Event Status Interrupt Register (ERR_RST_EVNT_ICSR) ................. 125 SPRU976...