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2-2 5-1 EVM Selection................................................................ 5-3 5-2 DSK-To-EVM Stackup Diagram ................................................. 5-3 6-1 Top Layer.................................................................... 6-4 6-2 Internal Plane 1 ............................................................... 6-5 6-3 Internal Plane 2............................................................... 6-5 6-4 Bottom Layer (Mirrored)........................................................ 6-6 Tables 2-1 Analog Input Pinout Description..................................................................................................2-3 2-2 ADC Reference Voltage................................................................................................................2-3 2-3 Jumper Settings ............................................................................................................................2-4 3-1 Digital Signal Pinout Description ................................................................................................3-2 4-1 Power Connector Pinout Description..........................................................................................4-1 viii Chapter 1 EVM Overview Each evaluation board is based on the equivalent ADC. All ADCs use a synchronous serial interface which can be simply interfaced to many microcontrollers using the SPI protocol. Each EVM also incorporates a stable voltage reference, and operational amplifier to ensure a low-noise voltage reference for the ADC. Topic Page 1.1 Features ..................................................... 1-2 1-1 Features 1.1 Features □ Evaluation board featuring one of the following: ■ TLC3578 ADC (order TLC3578 EVM) ■ TLC3574 ADC (order TLC3574 EVM) ■ TLC3548 ADC (order TLC3548 EVM) ■ TLC3544 ADC (order TLC3544 EVM) ■ TLC2578 ADC (order TLC2578 EVM) ■ TLC2574 ADC (order TLC2574 EVM) □ Onboard reference, with recommended buffer circuitry □ Suggested signal conditioning circuitry for 1 channel only 1-2 Chapter 2 Analog Interface Topic Page 2.1 Analog Interface Block Diagram................................2-2 2.2 Signal Conditioning ...........................................2-2 2.3 Single Supply Operation.......................................2-2 2.4 Physical Pinout Description ...................................2-3 2.5 ADC Reference Voltage........................................2-3 2.6 Configuration Options.........................................2-4 2-1 Analog Interface Block Diagram 2.1 Analog Interface Block Diagram A block diagram for the analog interface of the EVM is shown in Figure 2-1. Figure 2-1. Block Diagram The channels are arranged to comply with the EVM standard developed for data converters. This standard defines eight channels of analog I/O on each EVM module. 2.2 Signal Conditioning The facility exists for the signal connected to channel 0 to be conditioned via an operational amplifier. The amplifier present on the EVM operates from a dual power supply and is configured with a gain of +1. If signal conditioning is not required, it can easily be bypassed via a shorting bar. 2.3 Single Supply Operation Should the user wish to operate the amplifier from a single suply rail, this is also possible by simply removing the dual supply amplifier and replacing it with a suitable single supply alternative, for example the OPA353. The suggested procedure is detailed below: □ Carefully desolder amplifier, U1 □ Replace with a suitable single-supply alternative, for example TI part number OPA353UA □ Install appropriate resistor at R9 □ Install appropriate capacitor at C11 □ Install shorting bar at W1 2-2 Physical Pinout Description 2.4 Physical Pinout Description Samtec part numbers SSW-110-22-F-D-VS-K and TSM-110-01-T-DV-P provide a convenient 10-pin dual row header/socket combination at P1. This header/socket provides access to the analog input pins of the TLV2553/6. Consult Samtec at or 1-800-SAMTEC-9 for a variety of mating connector options. Table 2-1. Analog Input Pinout Description Pin Number Signal Description Header Socket P1.2 J1.2 CH0 Channel 0 input, can be direct from P1/J1 connector or through Op-Amp P1.4 J1.4 CH1 Channel 1 input, direct from P1/J1 connector P1.6 J1.6 CH2 Channel 2 input, direct from P1/J1 connector P1.8 J1.8 CH3 Channel 3 input, direct from P1/J1 connector P1.10 J1.10 CH4 Channel 4 input, direct from P1/J1 connector P1.12 J1.12 CH5 Channel 5 input, direct from P1/J1 connector P1.14 J1.14 CH6 Channel 6 input, direct from P1/J1 connector P1.16 J1.16 CH7 Channel 7 input, direct from P1/J1 connector P1.18 J1.18 REF- External Reference negative input P1.20 J1.20 REF+ External Reference positive input 2.5 Reference Voltage The accuracy of conversion from a SAR ADC depends directly upon the accuracy of the reference voltage. It is very important, therefore, that the re...